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FAN8042
5-CH Motor Driver
FAN8042 Features
* * * * * * * * 4-CH balanced transformerless (BTL) driver 1-CH (forward reverse) control DC motor driver Operating supply voltage (4.5 V ~ 13.2 V) Built in thermal shut down circuit (TSD) Built in channel mute circuit Built in power save mode circuit Built in TSD monitor circuit Built in 2-OP AMPs
Description
The FAN8042 is a monolithic integrated circuit suitable for a 5-CH motor driver which drives the tracking actuator, focus actuator, sled motor, spindle motor, and tray motor of the CDP/CAR-CD/DVDP systems.
48-QFP-1010E
Typical Application
* * * * Compact disk player Video compact disk player Car compact disk player Digital video disk player
Ordering Information
Device Package Operating Temperature -35C ~ +85C FAN8042 48-QFP-1010E
Rev. 1.0.0
(c)2001 Fairchild Semiconductor Corporation
Pin Assignments
OPOUT1
OPIN2+
OPIN2-
OPOUT2
OPIN1+
OPIN1-
GND
48
47
46
45
44
43
42
GND
41
40
39
38
37
IN1+ IN1OUT1 IN2+ IN2GND GND OUT2 IN3+
1 2 3 4 5 6 7 8 9
PVCC1 36 35 34 33 32 31 30 29 28 27 26 25
SVCC
VREF
PS
DO1+ DO1DO2+ DO2DO3+ GND GND DO3DO4+ DO4DO5+ DO5-
FAN8042
IN3- 10 OUT3 11 IN4+ 12
13 IN4-
14 OUT4
15 CTL
16 FWD
17 REV
18 GND
19 GND
20 SGND
21 MUTE123
22 MUTE4
23 TSD-M
24 PVCC2
2
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name IN1+ IN1- OUT1 IN2+ IN2- GND GND OUT2 IN3+ IN3- OUT3 IN4+ IN4- OUT4 CTL FWD REV GND GND SGND MUTE123 MUTE4 TSD-M PVCC2 DO5DO5+ DO4- DO4+ DO3- GND GND DO3+ I/O I I O I I O I I O I I O I I I I I O O O O O O O Pin Function Descrition CH1 op-amp input (+) CH1 op-amp input (-) CH1 op-amp output CH2 op-amp input (+) CH2 op-amp input (-) Ground Ground CH2 op-amp output CH3 op-amp input (+) CH3 op-amp input (-) CH3 op-amp output CH4 op-amp input (+) CH4 op-amp input (-) CH4 op-amp output CH5 motor speed control CH5 forward input CH5 reverse input Ground Ground Signal Ground Mute for CH1,2,3 Mute for CH4 TSD monitor Power supply voltage 2 (For CH4, CH5) CH5 drive output (-) CH5 drive output (+) CH4 drive ouptut (-) CH4 drive output (+) CH3 drive ouptut (-) Ground Ground CH3 drive output (+)
3
Pin Definitions (Continued)
Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name DO2- DO2+ DO1- DO1+ PVCC1 PS OPOUT2 OPIN2- OPIN2+ GND GND VREF SVCC OPOUT1 OPIN1- OPIN1+ I/O O O O O I O I I I O I I Pin Function Descrition CH2 drive ouptut (-) CH2 drive output (+) CH1 drive ouptut (-) CH1 drive output (+) Power supply voltage 1 (FOR CH1, CH2, CH3) Power save Normal op-amp2 output Normal op-amp2 input (-) Normal op-amp2 input (+) Ground Ground Bias voltage input Signal & OPAMPs supply voltage Normal op-amp1 output Normal op-amp1 input (-) Normal op-amp1 input (+)
4
Internal Block Diagram
OPIN1+ OPIN1- OPOUT1 SVCC 48 47 46 45 VREF 44 GND 43 GND OPIN2+ OPIN2- OPOUT2 42 41 40 39 PS 38 PVCC1 37
IN1+
1
40K
POWER SAVE
36
DO1+
IN1-
2
10K 10K
35
DO1-
OUT1
3
10K
40K 40K 10K 10K 40K 40K 40K 10K 40K 10K 10K
40K
34
DO2+
IN2+
4
10K
33
DO2-
IN2-
5
32
40K
DO3+
GND
6
10K 40K 40K 10K 10K 40K
31
GND
GND
7
40K
30
GND
OUT2
8
10K 10K 40K
29
DO3-
IN3+
9
10K
40K
28
DO4+
IN3- 10
10K 40K
27
DO4-
OUT3 11
S W
M S C
+ MUTE123
D
26
DO5+
D
IN4+
12
MUTE4 TSD-M
25
DO5-
13 IN4-
14 OUT4
15 CTL
16 FWD
17 REV
18 GND
19 GND
20 SGND
21
22
23
24
MUTE4 TSD-M PVCC2 MUTE123
Note. Detailed circuit of the output power amp
40K 10K From input opamp 10K Pref 10K - + 40K 40K + - 10K 40K Pref1 is almost PVCC1 / 2 Pref2 is almost PVCC2 / 2 DO-
DO+
Vref
5
Equivalent Circuits
Description Pin No Internal Circuit
VCC
VCC
2K 2K
2 10 5 13
BTL INPUT
1,4,9,12, 2,5,10,13
1 9
4 12
VCC
5K
VCC
5K
41
OP AMP INPUT
40,41
40
VCC
1K 5K
VCC
VREF
44
44
1K
VCC
VCC
OP AMP OUTPUT
3,8,11,14
3 11
8 14
6
Equivalent Circuits
Description Pin No Internal Circuit
VCC
0.05k
OP OUT
39,46
39 46
0.05k
VCC
20K
MUTE123
21
21
50K 50K
VCC
MUTE4
22
22
1K
39K
TSD-M
23
23
20k
7
Equivalent Circuits
Description Pin No Internal Circuit
VCC
100k
PS
38
38
50K 50K
VCC
30K
FWD,REV
16,17
17 16
30K 30K
30K
VCC VCC
freewheeling diode
OUTPUT
27,29,33,35, 28,32,34,36
27 29 40 33 35
28 32 34 36
40K 7K
parastic diode
freewheeling diode
VCC
VCC
OUTPUT
25,26
25 26
60K
parastic diode
7K
8
Absolute Maximum Ratings ( Ta=25C)
Parameter Maximum Supply Voltage Power Dissipation Operating Temperature Storge Temperature Maximum Output Current Symbol SVCCMAX PVCC1 PVCC2 PD TOPR TSTG IOMAX Value 18 18 18 2.3note -35 ~ +85 -55 ~ +150 1 Unit V V V W C C A
Notes: 1. When mounted on 70mm x 70mm x 1.6mm PCB 2. Power dissipation reduces 24mW/C for using above TA = 25C 3. Do not exceed PD and SOA
Pd (mW) 3,000 2,000
1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [C]
Recommended Operating Conditions ( Ta=25C)
Parameter Operating Supply Voltage Symbol SVCC PVCC1 PVCC2 Min. 4.5 4.5 4.5 Typ. Max. 13.2 13.2 13.2 Unit V V V
9
Electrical Characteristics
(SVCC =5V, PVCC1 = PVCC2 = 11V, TA = 25C, unless otherwise specified) Parameter Quiescent circuit current Power save on current Power save on voltage Power save off voltage Mute123 on voltage Mute123 off voltage Mute4 on voltage Mute4 off voltage BTL DRIVER CIRCUIT Output offset voltage Maximum output voltage 1 Maximum output voltage 2 Closed-loop voltage gain Ripple rejection ratio Slew rate INPUT OPAMP CIRCUIT Input offset voltage 1 Input bias current 1 High level output voltage 1 Low level output voltage 1 Output sink current 1 Output source current 1 Common mode input range1 Open loop voltage gain 1 Ripple rejection ratio 1 Common mode rejection ratio 1 Slew rate 1 VOF1 IB1 VOH1 VOL1 ISINK1 ISOU1 VICM1 GVO1 RR1 CMRR1 SR1 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p RL = 50 RL = 50 -10 4.4 1 1 -0.3 4.7 0.2 2 2 80 65 80 1.5 +10 400 0.5 4.0 mV nA V V mA mA V dB dB dB V/s VOO VOM1 VOM2 AVF RR SR VIN = 2.5V RL = 10 RL = 18 VIN = 0.1Vrms VIN = 0.1Vrms, f = 120Hz Square, Vout = 4Vp-p -100 7.5 8.5 16.8 1 9.0 9.5 18 60 2 +100 19.2 mV V V dB dB V/s Symbol ICC IPS VPSON VPSOFF VMON123 VMOFF123 VMON4 VMOFF4 Conditions Under no-load Under no-load (Note1) Pin38 = Variation Pin38 = Variation Pin21 = Variation Pin21 = Variation Pin22 = Variation Pin22 = Variation Min. 2 2 2 Typ. 30 Max. 1 0.5 0.5 0.5 Unit mA mA V V V V V V
Note: 1. When the voltage of the pin38 is below 0.5V then the power save circuit cuts off the main bias current, so that the whole circuits are disabled (whole circuits are "drive circuit ", "input op amp circuit " and "nomal op amp circuit ")
10
Electrical Characteristics (Continued)
(SVCC = 5V, PVCC1 = PVCC2 = 11V, TA = 25C, unless otherwise specified) Parameter NORMAL OP AMP CIRCUIT 1 Input offset voltage 2 Input bias current 2 High level output voltage 2 Low level output voltage 2 Output sink current 2 Output source current 2 Common mode input range 2 Open loop voltage gain 2 Ripple rejection ratio 2 Common mode rejection ratio 2 Slew rate 2 NORMAL OP AMP CIRCUIT 2 Input offset voltage 3 Input bias current 3 High level output voltage 3 Low level output voltage 3 Output sink current 3 Output source current 3 Open loop voltage gain 3 Ripple rejection ratio 3 Common mode rejection ratio 3 Slew rate 3 TRAY DRIVE CIRTUIT Input high level voltage Input low level voltage Output voltage 1 Output voltage 2 Output voltage 3 Output load regulation Output offset voltage 1 Output offset voltage 2 VIH VIL VO1 VO2 VO3 VRL VOO1 VOO2 PVCC2 = 11V, VCTL = 3V, RL = 45 PVCC2 = 13V, VCTL = 4.5V, RL = 45 PVCC2 = 11V, VCTL = 1.5V, RL = 10 VCTL=3V, IL=100mA 400mA VIN = 5V, 5V VIN = 0V, 0V 2 2.5 -40 -40 6 9 3 300 0.5 3.5 700 +40 +40 V V V V V mV mV mV VOF3 IB3 VOH3 VOL3 ISINK3 ISOU3 GVO3 RR3 CMRR3 SR3 RL = 50 RL = 50 VIN =-75dB VIN= -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p -15 3 10 10 3.8 1.0 80 65 80 1.5 +15 400 1.5 mV nA V V mA mA dB dB dB V/s VOF2 IB2 VOH2 VOL2 ISINK2 ISOU2 Vicm2 GVO2 RR2 CMRR2 SR2 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p RL = 50 RL = 50 -10 4.4 2 2 -0.3 4.7 0.2 4 4 80 65 80 1.5 +10 400 0.5 4.0 mV nA V V mA mA V dB dB dB V/s Symbol Conditions Min. Typ. Max. Unit
11
Application Information
1. Thermal Shutdown
* When the chip temperature reaches to 160C by abnormal condition, then the TSD circuit is activated. * This shut down the bias current of the output drivers, and all the output drivers are in cut-off state. Thus the chip temperature begin to decrease. * when the chip temperature falls to 135C, the TSD circuit is deactivated and the output drivers are normally operated. * The TSD circuit has the hysteresis temperature of 25C.
SVCC IREF R1 Q0 R2 Hysteresis Ihys R3 Output driver bias
2. CH MUTE Function
* When the pin21,22 is high, the TR Q1 is turned on and Q2 is off, so the bias circuit is enabled. On the other hand, when the pin21,22 is Low (GND) , the TR Q1 is turned off and Q2 is on, so the bias circuit is disabled. * That is, this function will cause all the output drivers to be in mute state. * Truth table is as follows; Pin 21,22 High Low FAN8042 Mute-Off Mute-On
Bias blocks 3-Ch BTL
SVCC
21
22 Q1
Q2
3. Power Save Function
* When the pin38 is high, the TR Q3 is turned on and Q4 is off, so the bias circuit is enabled. On the other hand, when the pin38 is Low (GND) , the TR Q3 is turned off and Q4 is on, so the bias circuit is disabled. * That is, this function keeps all the circuit blocks of the chip off , thus the low power quiescent state is established * Truth table is as follows; Pin38 High Low FAN8042 Power Save Off Power Save On
SVCC Main Bias
38 Q3
Q4
12
4. Tsd Monitor Function
* PIN23 is TSD monitor pin which detects the state of the TSD block and generates the TSD-monitor signal. * In normal state Q5 is turned on, so Q6 is turned off. on the otherhand, When the TSD block is is activated then Q5 is turned off, so the voltage of pin23 is low. * Truth table is as follows pin23 High Low FAN8042 Tsd Off Tsd On
5. Focus, Tracking Actuator, Spindle, Sled Motor Drive Part
R2 R1 OPin+ OPin1 2 4 5 9 12 + - Vin R1 Vp R2 R1 PVCC1(PVCC2) Dp 60k + 62k Qp - Vp 10 13 - + R2 R2 + - R2 M DON 27 29 33 35 DOP 28 32 34 36
3
8 Vref
11 14 44
* The voltage, Vref is the reference voltage given by the external bias voltage of the pin 44. * The input signal (Vin) through pins 1,4,9, 12 is amplified one time and then fed to the output stage. (assume that input opamp was used as a buffer) * The total closed loop voltage gain is as follows
Vin = Vref + V DOP = Vp + 4 V DON = Vp - 4 V Vout = DOP - DON = 8 V Vout Gain = 20 log ------------ = 20 log 8 = 18dB V
* If you want to change the total closed loop voltage gain, you must use the input opamp as an amplifier * The output stage is the balanced transformerless (BTL) driver. * The bias voltage Vp is expressed as ;
62k Vp = ( PVCC1 - VDp - VcesatQp ) x ------------------------- + VcesatQp 60k + 62k = PVCC1 - VDp + VcesatQp + VcesatQp -------------------------------------------------------------------------1.97
----------
(1)
13
6. Tray, Changer,panel Motor Drive Part
out 1 25
M
out 2 26
D
D
LEVEL SHIFT 6.5V CTL 15 S.W 0 3.25V VCTL M.S.C V(out1,out2)
IN
IN
FWD 16
REV 17
* Rotational direction control The forward and reverse rotational direction is controlled by FWD (pin16) and REV (pin17) and the input conditions are as follows. INPUT FWD H H L L REV H L H L OUT 1 Vp H L OUTPUT OUT 2 Vp L H State Brake Forward Reverse High impedance
* Where Vp(Power reference voltage) is approximately about 3.75V at PVCC2=8V according to equation (1). * Motor speed control (When SVCC=PVCC2=8V) - The almost maximum torque is obtained when the VCTL is open. - If the voltage of the pin15 is 0V, the motor will not operate. - When the control voltage of the pin15 is between 0 and 3.25V, the differential output voltage(V(out1,out2)) is about two times of control voltage. Hence, the control to the differential output gain is two. - When the control voltage is greater than 3.25V, the output voltage is saturated at the 6.5V because of the output swing limitation.
14
Test Circuits
VCC OP-AMP
IN+ INOUT
VREF
OP-AMP
IN+ INOUT
PVCC1
V PS
48 OPIN1+ 1 IN+ IN1+
47 OPIN1-
46 OPOUT1
45 SVCC
44 VREF
43 GND
42 GND
41 OPIN2+
40
39
38 PS
37 PVCC1 DO1+ 36
OPIN2- OUTPUT2
RL1
2 IN1DO135
OP-AMP
INOUT
3
OUT1
DO2+
34
RL2
4 IN+ IN2+ DO233
OP-AMP
INOUT
5
IN2-
DO3+
32
6
GND
7
FAN8042
GND
31
RL3
GND 30
GND
8
OUT2
DO3-
29
9 IN+
IN3+
DO4+
28
RL4
10 IN3DO427
OP-AMP
INOUT
11
OUT3
DO5+ DO5OUT4 14 CTL 15 FWD 16 REV 17 GND 18 GND 19 SGND 20 MUTE 123 21 MUTE4 22 TSD-M 23 PVCC2 24
26
RL5
25
IN+
12
IN4+ IN413
OP-AMP
INOUT
V CTL
V FWD
V REV
V MU123
V MU4 PVCC2
OP-AMP
IN+ INOUT
SW1
SW2 VCC
SW4 V AC V DC VA V PULSE VB SW3
RL
15
Typical Application Circuits 1
[Voltage mode control mode]
SVCC POWER SAVE
PVCC1
48
47
46
45
44 VREF
43 GND
42 GND
41
40
39
38
37 PVCC1 DO1+ 36
OPIN1+ OPIN1- OPOUT1 SVCC 1 IN1+
OPIN2+ OPIN2- OUTPUT2 PS
FOCUS
35
2
IN1-
DO1-
3
OUT1
DO2+
34
TRACKING
4 IN2+ DO233
5
IN2-
DO3+
32
6
GND
7
GND
FAN8042
GND
31
M
GND 30
SLED
8
OUT2
DO3-
29
9
IN3+
DO4+
28
M
10 IN3DO427
SPINDLE
11
OUT3
DO5+ DO5OUT4 14 CTL 15 FWD 16 REV 17 GND 18 GND 19 SGND 20 MUTE 123 21 MUTE4 TSD-M PVCC2 22 23 24
26
M
12 IN4+ IN413 25
TRAY
PVCC2 TSD MONITOR
VREF FOCUS TRACKING SLED INPUT INPUT INPUT SPINDLE INPUT TRAY TRAY CONTROL INPUT
SPINDLE MUTE FOCUS, TRACKING & SLED MUTE
[SERVO PRE AMP]
[CONTROLER]
Notes:
* Radiation pin is connected to the internal GND of the package. * Connect the pin to the external GND * This device that named FAN8042 is the same as FAN8034, and this datasheet was made for particular customers
16
Typical Application Circuits 2
[Differential PWM control mode ]
SVCC POWER SAVE
PVCC1
48
47
46
45
44 VREF
43 GND
42 GND
41
40
39
38 PS
37 PVCC1 DO1+ 36
OPIN1+ OPIN1- OPOUT1 SVCC 1 IN1+
OPIN2+ OPIN2- OUTPUT2
FOCUS
35
2
IN1-
DO1-
3
OUT1
DO2+
34
TRACKING
4 IN2+ DO233
5
IN2-
DO3+
32
6
GND
7
GND
FAN8042
GND
31
M
GND 30
SLED
8
OUT2
DO3-
29
9
IN3+
DO4+
28
M
10 IN3DO427
SPINDLE
11
OUT3
DO5+ DO5OUT4 14 CTL 15 FWD 16 REV 17 GND 18 GND 19 SGND 20 MUTE 123 21 MUTE4 TSD-M PVCC2 22 23 24
26
M
12 IN4+ IN413 25
TRAY
PVCC2 TSD MONITOR
VREF FOCUS TRACKING INPUT INPUT SLED INPUT SPINDLE INPUT TRAY TRAY CONTROL INPUT
SPINDLE MUTE FOCUS, TRACKING & SLED MUTE
[SERVO PRE AMP]
[CONTROLER]
17
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 9/4/01 0.0m 001 Stock#DSxxxxxxxx 2001 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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